Technological developments related to the formation of a gate electrode using a metal gate electrode and a high dielectric constant (High-K) insulation film have been actively carried out in recent years in order to realize further high performance and low power consumption of a semiconductor device, especially a metal oxide semiconductor field effect transistor (MOSFET). With the adoption of such a gate stack, gate depletion that may occur at conventional polysilicon gate electrode is suppressed and a leak current (gate tunnel leak current) caused by quantum tunnel effect is reduced. As a result, a drive current of the MOSFET may be increased and switching speed of semiconductor circuit may be increased.
Japanese Patent Application No. 2011-49282 (refer to FIG. 1 to FIG. 19) is one example, wherein a method is described for manufacturing a semiconductor device having on the same substrate, a metal-oxide-nitride-oxide-silicon (MONOS) (e.g., a metal/silicon oxide film/silicon nitride film/silicon oxide film/silicon) type nonvolatile memory relatively excellent in reliability, a high voltage metal insulator semiconductor field effect transistor (MISFET), and a low voltage MISFET using a metal gate and a High-K insulation film in a gate structure. In this method, cell structures of the MONOS-type nonvolatile memory and the high voltage MISFET, and an opening for a metal gate electrode of the low voltage MISFET are formed, and thereafter a metal film that serves as a metal gate is deposited on these. Then, the metal film is polished chemically and mechanically (i.e., chemical mechanical polishing (CMP)) to form a metal gate electrode as exposed. Thereafter, contact plugs each connected to the source and drain of each transistor are formed, and further a wiring layer and an interlayer insulation film are formed thereon by the known Damascene process.
However, when the metal gate electrode is formed in such a conventional method, a difference locally occurs in polishing amount due to a difference in pattern density between various cell areas (e.g., a memory cell area and a logic cell area) upon subjecting the metal film to CMP. As a result, there is a possibility that the flatness of a substrate surface (in a substrate plane) will be damaged, and if the contact plugs are formed thereafter, the desired performance and reliability of a resulting product cannot be achieved. If further miniaturization is desired, the influence of such deterioration in planarity can be more remarkable.